1. Field of the Invention
The invention relates in general to a computer field, and more particularly to a repair method and device for an abnormal-erase memory block of a non-volatile flash memory.
2. Description of the Related Art
A non-volatile flash memory (e.g., a NAND flash), being advantaged by having a large capacity, a fast access speed and a low cost per unit capacity, is prevalent as a carrier for storing data in embedded devices.
Although offering the above advantages, the NAND flash nevertheless suffers from certain drawbacks. For example, a main drawback of the NAND flash is that the NAND flash has a less satisfactory reliability. To ensure intactness of user information, software is implemented to remedy the hardware insufficiency. With respect to the less satisfactory reliability of the NAND flash, bad blocks are a most critical issue that draws much attention.
In fact, erase, write and read operations of the NAND flash memory are similarly unreliable, and may also produce errors. However, probabilities of errors in erase, write and read operations are rather small and are frequently neglected. In the occurrence of errors in read and write operations, intactness of data remains undamaged as a result of protection provided by an error correcting code (ECC). A NAND flash is generally divided into memory blocks, each being divided into several pages. Read and write operations are performed based on a unit of pages. Each page is divided into a main region and a spare region. The main region is larger in size and stores user data; the spare region is smaller and stores the ECC. Only in a page storing user data in the main region, the ECC is calculated and stored in the spare region. Substantially, a write operation sets logic “1” bits in a to-be-written block to logic “0”, whereas an erase operation conversely sets logic “0” bits in a to-be-erased block to logic “1”. The ECC is not calculated in blank pages subsequent to the erased page, and the spare region maintains the status of all the logic “1” bits.
Assuming an erase operation is not protected by the ECC when an error occurs in the erase operation or when an erase process encounters an unexpected power-off, inexplicable situations are often caused if a system reads related information of the last erroneous erase operation. Not only user experience is degraded, but also catastrophic outcomes such as a system crash or a system standstill may be resulted. Therefore, there is a need for a solution that provides satisfactory reliability to an erase operation of the NAND flash.